Maximizing Performance of Microelectronic Thermoelectric Generators With Parasitic Thermal and Electrical Resistances
Maximizing Performance of Microelectronic Thermoelectric Generators With Parasitic Thermal and Electrical Resistances
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DOI：
10.1109/ted.2021.3067624
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发表时间：
2021-05
影响因子：
3.1
通讯作者：
Ruchika Dhawan;Prabuddha Madusanka;G. Hu;K. Maggio;H. Edwards;Mark Lee
中科院分区：
文献类型：
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作者：
Ruchika Dhawan;Prabuddha Madusanka;G. Hu;K. Maggio;H. Edwards;Mark Lee
微电子热电（TE）发电机（$\mu $TEG），这是一个潜在的解决方案，以供电能源自主集成电路（IC），往往是性能有限的，因为寄生电阻和热阻的$\mu $ TEG电路。寄生性能损失可以是特别严重的$\mu $TEG使用的材料具有相对较低的TE品质因数，如硅（Si）。在这种情况下，必须特别注意优化整个$\mu $ TEG电路，而不仅仅是TE材料的特性。在这里，$\mu $ TEG器件性能的定量模型的开发，其中包括所有重要的电气和热寄生通常遇到的IC兼容的$\mu $TEG。该模型给出了一对耦合的二次方程，可以通过解析或数值求解来确定发电量和效率。对于给定的寄生电阻和材料特性值，该模型表明，TE元件所占的横截面积与每个热电堆的热流的总横截面积的比率（在这里称为填充分数）可以被设计为使功率或效率最大化，但不能同时使两者最大化。对于实际的材料和器件参数，最佳填充分数通常只有1%-10%，低于许多$\mu $ TEG设计中使用的填充分数。该模型占报告的发电量的一些例子$\mu $ TEGs，并提供指导，对显着的性能改善。
Microelectronic thermoelectric (TE) generators ( $\mu $ TEGs), which are one potential solution to powering energy autonomous integrated circuits (ICs), are often performance limited because of parasitic electrical and thermal resistances in the $\mu $ TEG circuit. Parasitic performance loss can be particularly severe for $\mu $ TEGs using materials with relatively low TE figure-of-merit, such as silicon (Si). In such cases, careful attention must be paid to optimizing the entire $\mu $ TEG circuit, not just the TE material properties. Here, a quantitative model of $\mu $ TEG device performance is developed that includes all significant electrical and thermal parasitics commonly encountered in IC-compatible $\mu $ TEGs. The model gives a pair of coupled quadratic equations that can be analytically or numerically solved to determine power generation and efficiency. For given parasitic resistance and material property values, the model shows that the ratio (called here the packing fraction) of cross-sectional area occupied by TE elements to total cross-sectional area for heat flow per thermopile can be designed to maximize either power or efficiency, but not both simultaneously. For realistic material and device parameters, the optimum packing fraction is often only 1%–10%, lower than what is used in many $\mu $ TEG designs. The model accounts for the reported power generation of some example $\mu $ TEGs and provides guidance toward significant performance improvement.