Accelerating Large Scale GCN Inference on FPGA
Accelerating Large Scale GCN Inference on FPGA
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DOI：
10.1109/fccm48280.2020.00074
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发表时间：
2020-05
期刊：
影响因子：
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通讯作者：
Bingyi Zhang;Hanqing Zeng;V. Prasanna
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文献类型：
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作者：
Bingyi Zhang;Hanqing Zeng;V. Prasanna
我们提出了一种算法架构协同优化框架来加速 FPGA 上的大规模 GCN 推理。我们首先执行数据分区，以适应FPGA有限的片上存储器中的每个分区。然后，我们使用由稀疏化和节点重新排序组成的两阶段预处理算法。第一阶段（稀疏化）通过合并公共邻居节点来消除高度节点的边缘连接。第二阶段（重新排序）有效地对密集连接的邻域进行分组，以改善片上数据的重用。结合上述算法优化，我们提出了一种 FPGA 架构来高效执行 GCN 的两个关键计算内核——特征聚合和权重变换。我们在最先进的 FPGA 设备上评估我们的设计。与多核和 GPU 基准相比，我们的设计将推理延迟分别降低了高达 30 美元和 2 美元。
We propose an algorithm-architecture co-optimization framework to accelerate large-scale GCN inference on FPGA. We first perform data partitioning to fit each partition in the limited on-chip memory of FPGA. Then, we use the two-phase pre-processing algorithm consisting of sparsification and node reordering. The first phase (sparsification) eliminates edge connections of high-degree nodes by merging common neighbor nodes. The second phase (re-ordering) effectively groups densely connected neighborhoods to improve on-chip data reuse. Incorporating the above algorithmic optimizations, we propose an FPGA architecture to efficiently execute the two key computational kernels of GCN - feature aggregation and weight transformation. We evaluate our design on a state-of-the-art FPGA device. Compared with multi-core and GPU baselines, our design reduces the inference latency by up to $30 \times $ and $2 \times $ respectively.