Employing radiation hardness by design techniques with commercial integrated circuit processes
Employing radiation hardness by design techniques with commercial integrated circuit processes
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通过商业集成电路工艺的设计技术采用辐射硬度
DOI：
10.1109/dasc.1997.635027
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发表时间：
1997
期刊：
影响因子：
--
通讯作者：
D. Alexander
中科院分区：
文献类型：
--
作者：
D. Mavis;D. Alexander
尽管工艺硬化仍然是在高密度集成电路（IC）中实现抗辐射性的优选方法，但是最近对在商业0.81 μ/mCMOS制造工艺中制造的专门设计的门阵列单元的硬度的研究已经证明了大于100 krad（Si）的总电离剂量硬度，没有单粒子闭锁，和大于50 MeV-cm/sup 2//mg的单粒子翻转LET（线性能量转移）（LET）阈值。这项工作表明，有可能实现廉价的ASIC（专用集成电路）的适度的复杂性和辐射耐受性与商业IC工艺。
Though process hardening remains the preferred method for achieving radiation hardness in high density integrated circuits (ICs), recent investigations into the hardness of specially designed gate array cells fabricated in a commercial 0.81 /spl mu/m CMOS fabrication process have demonstrated greater than 100 krads (Si) total ionizing dose hardness, no single event latchup, and single event upset LET (linear energy transfer) (LET) thresholds greater than 50 MeV-cm/sup 2//mg. This work suggests that it is possible to achieve inexpensive ASICs (Application Specific Integrated Circuits) of modest complexity and radiation tolerance with commercial IC processes.