Experiences with Performance Measurement and Modeling of a Processor Array
Experiences with Performance Measurement and Modeling of a Processor Array
复制标题
处理器阵列性能测量和建模的经验
DOI：
10.1109/tc.1983.1676120
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发表时间：
1983
影响因子：
3.7
通讯作者：
Wolfgang Kleinöder
中科院分区：
文献类型：
--
作者：
H. Fromm;Uwe Hercksen;U. Herzog;Karl;R. Klar;Wolfgang Kleinöder
技术的发展为形成紧密合作的大型处理器群提供了机会。在分解应用程序和子任务分配给不同的处理器时，我们不仅期望高吞吐量，而且希望尽可能快地执行每个单独的需求。这些领域的性能水平受到硬件互连结构和通信软件的强烈影响。
The evolution of technology provides the opportunity of forming large processor ensembles working closely together. When decomposing application programs and assigning subtasks to different processors we expect not only high throughput, but also the fastest possible execution of each individual demand. The level of performance in these areas is strongly influenced by the hardware interconnection structure and by the communication software.