Three-dimensional integration technology based on reconfigured wafer-to-wafer and multichip-to-wafer stacking using self-assembly method
Three-dimensional integration technology based on reconfigured wafer-to-wafer and multichip-to-wafer stacking using self-assembly method
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DOI：
10.1109/iedm.2009.5424353
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发表时间：
2009-12
期刊：
影响因子：
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通讯作者：
T. Fukushima;E. Iwata;Y. Ohara;A. Noriki;K. Inamura;Kang-wook Lee;J. Bea;Tetsu Tanaka;M. Koyanagi
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文献类型：
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作者：
T. Fukushima;E. Iwata;Y. Ohara;A. Noriki;K. Inamura;Kang-wook Lee;J. Bea;Tetsu Tanaka;M. Koyanagi
我们使用具有液体表面张力的芯片自组装技术演示了两种类型的三维 (3D) 集成。在重新配置的晶圆到晶圆3D集成中，许多不同尺寸的具有带/不带TSV（硅通孔）的In/Au微凸块的芯片通过自组装以背对面的方式临时放置在重新配置的晶圆上。然后，可以将许多芯片同时转移到LSI晶圆上，该LSI晶圆完全面对重新配置的晶圆，并且具有与自组装芯片相同的微凸块阵列图案。另一方面，在多芯片到晶圆3D集成中，具有尺寸为5μm和10μm的In/Au微凸块的Si芯片以面对面的方式直接自组装在具有相同In/Au微凸块的另一LSI晶圆上。自组装后，这些芯片可以在 200°C 下粘合，无需施加机械压力。在这两种基于自组装的 3D 集成中，芯片都通过微凸块到微凸块互连精确对准并键合到 LSI 晶圆上。我们利用自组装芯片和晶圆之间形成的微凸块菊花链获得了良好的电气特性。
We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by self-assembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously transferred to an LSI wafer that is fully faced with the reconfigured wafer and has the same microbump array patterns to the self-assembled chips. On the other hand, in multichip-to-wafer 3D integration, Si chips having In/Au microbumps with sizes of 5 µm and 10 µm were directly self-assembled on another LSI wafer having the same In/Au microbumps in a face-to-face manner. After the self-assembly, these chips can be bonded at 200 °C without applying mechanical pressure. In both of the self-assembly-based 3D integration, the chips were precisely aligned and bonded to the LSI wafers through the microbump-to-microbump interconnection. We obtained good electrical characteristics using the microbump daisy chains formed between the self-assembled chips and the wafers.