OS-controlled cache predictability for real-time systems
OS-controlled cache predictability for real-time systems
复制标题
DOI：
10.1109/rttas.1997.601360
复制
发表时间：
1997-06
期刊：
影响因子：
--
通讯作者：
J. Liedtke;Hermann Härtig;M. Hohmuth
中科院分区：
文献类型：
--
作者：
J. Liedtke;Hermann Härtig;M. Hohmuth
已发明了缓存技术，以使现代处理器具有广泛的高速缓存结构，可在实时系统中有用，在该系统中，任务开关干扰缓存工作集，因此使执行时间无法预测。本文介绍了一种OS控制的应用程序透明的高速缓存技术。可以将结果分区透明地分配给任务以供其独家使用。在CACHE分区技术中发现的主要缺点，即浪费了CPU中的记忆力和在CPU内的关键性能路径上的增加，可以使用记忆着色技术或需要在现代CPU的芯片或绩效关键路径中进行更改的内存着色技术。在实时系统中常用的一种简单的滤波器算法，矩阵 - 培养算法和两者的相互作用均已分析有关缓存诱导的最坏情况的惩罚。最严重的罚款是针对不同广泛使用的高速缓存架构的。描述了有关缓存体系结构对最坏情况执行的影响的一些见解。
Cache-partitioning techniques have been invented to make modern processors with an extensive cache structure useful in real-time systems where task switches disrupt cache working sets and hence make execution times unpredictable. This paper describes an OS-controlled application-transparent cache-partitioning technique. The resulting partitions can be transparently assigned to tasks for their exclusive use. The major drawbacks found in other cache-partitioning techniques, namely waste of memory and additions on the critical performance path within CPUs, are avoided using memory coloring techniques that do nor require changes within the chips of modern CPUs or on the critical path for performance. A simple filter algorithm commonly used in real-time systems, a matrix-multiplication algorithm and the interaction of both are analysed with regard to cache-induced worst case penalties. Worst-case penalties are determined for different widely-used cache architectures. Some insights regarding the impact of cache architectures on worst-case execution are described.