A 90nm 32-mb phase change memory with flash SPI compatibility
A 90nm 32-mb phase change memory with flash SPI compatibility
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具有闪存 SPI 兼容性的 90nm 32-mb 相变存储器
DOI：
10.1109/imw.2014.6849379
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Sourabh Sharma
中科院分区：
文献类型：
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作者：
W. Hokenmaier;D. Labrecque;R. Jurasek;V. Butler;C. Scoville;Aaron Willey;S. Loeffler;Yuanxing Li;Sourabh Sharma
32mb相变存储器采用90nm 6-Metal工艺实现。擦除速度为10.0 mb /s，程序速度为35.6 mb /s。在85°C下，细胞保留时间为10年，细胞耐力为109次循环。25F2蘑菇电池相变存储器采用平面晶体管。采用ECC解决方案校正128位数据总线中的两位，芯片面积开销为12%。该部件符合用于NOR闪存部件的SPI规范。字和位冗余用于修复有缺陷的位。使用一种技术将保险丝信息存储在PCM元件中，该技术提高了保险丝信息的可靠性，使其能够承受焊接周期。使用了一种方法来确保在上电时正确下载保险丝，即使具有异步上电行为。开发电源岛是为了在待机模式下禁用写入所需的高压电源和数据路径所需的外设逻辑，从而减少待机电流。
A 32-Mb Phase Change Memory is realized in a 90nm 6-Metal process. An erase speed of 10.0-Mb/second and program speed of 35.6-Mb/second is achieved. The cell retention is interpolated to be 10 years at 85°C and cell endurance is measured to be 109 cycles. The 25F2 mushroom cell phase change memory utilizes a planar transistor. An ECC solution is employed to correct two bits out of a 128-bit data bus, with a 12% chip area overhead. The part is compliant with an SPI spec used for a NOR flash part. Word and bit redundancy are used for repairing defective bits. Fuse information is stored in PCM elements using a technique that increases the reliability of the fuse information, enabling it to withstand a solder cycle. A method is used to ensure proper fuse download at power up, even with the asynchronous power on behavior. Power islands are developed to disable both the high voltage supply needed for writes and peripheral logic needed for the datapath when in a standby mode, thereby reducing standby current.