A FIFO ring performance experiment
A FIFO ring performance experiment
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FIFO 环性能实验
DOI：
10.1109/async.1997.587181
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发表时间：
1997
期刊：
影响因子：
--
通讯作者：
J. Lexau
中科院分区：
文献类型：
--
作者：
C. E. Molnar;I. W. Jones;William S. Coates;J. Lexau
我们描述了一种高速 FIFO 电路，旨在比较异步 FIFO 与使用相同数据路径的时钟移位寄存器的性能。 FIFO 使用类似脉冲的协议来沿着管道推进数据。使用该协议需要仔细管理其控制电路内的电路延迟，以及控制信号与捆绑数据移动的协调。在使用 hSpice 的仿真中，异步电路的吞吐量与两相时钟设计的吞吐量相匹配。我们使用 MOSIS 的 0.6 微米设计规则制造了 50 个零件。我们根据测试测量估计，内部 FIFO 级可支持的最大吞吐量为 50 个芯片中最慢的芯片每秒 9.3 亿个数据项，到最快的芯片每秒 11.26 亿个数据项。当 3.3V 标称 Vdd 从 1.67V 变化到超过 4.8V 时，所有 50 个样本都正确运行，并且随着电源电压的变化，运行速度和功率也会相应变化。
We describe a high-speed FIFO circuit intended to compare the performance of an asynchronous FIFO with that of a clocked shift register using the same data path. The FIFO uses a pulse-like protocol to advance data along the pipeline. Use of this protocol requires careful management of circuit delays within its control circuits, as well as in the coordination of control signals with movement of bundled data. In simulations using hSpice, the throughput of the asynchronous circuit matches that of a two-phase clocked design. We fabricated 50 parts through MOSIS using their 0.6 micron design rules. We estimate from test measurements that the internal FIFO stages could support a maximum throughput from 930 million data items per second for the slowest of the 50 chips to 1126 million per second for the fastest chip. All 50 samples operated correctly as 3.3 V nominal Vdd varied from 1.67 V to over 4.8 V, with corresponding changes in operating speed and power as the supply voltage changed.