LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics
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DOI：
10.1145/3640464
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发表时间：
2022-09
影响因子：
2
通讯作者：
Zhiqiang Que;Hongxiang Fan;Marcus Loo;He Li;Michaela Blott;M. Pierini;A. Tapper;W. Luk
中科院分区：
文献类型：
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作者：
Zhiqiang Que;Hongxiang Fan;Marcus Loo;He Li;Michaela Blott;M. Pierini;A. Tapper;W. Luk
这项工作提出了一种新的低延迟图神经网络（LL-GNN）粒子探测器设计的可重构架构，提供了前所未有的低延迟性能。将基于FPGA的GNN扩展到粒子探测器中是一个独特的挑战，因为它需要亚微秒的延迟来部署网络进行在线事件选择，在CERN大型强子对撞机实验的1级触发器中每秒数百TB的数据速率。本文提出了一种新的基于外积的矩阵乘法方法，该方法通过利用结构化邻接矩阵和列优先数据布局来增强。此外，我们提出了一个自定义的代码转换矩阵乘法运算，它利用结构化稀疏模式和邻接矩阵的二进制特征，以减少延迟和提高硬件效率。此外，融合步骤被引入，以通过消除不必要的边界来进一步减少端到端设计延迟。此外，提出了一种特定于GNN的算法-硬件协同设计方法，该方法不仅可以找到具有更好延迟的设计，而且可以在给定延迟约束下找到高精度设计。为了促进这一点，已经设计并开源了这种低延迟GNN硬件架构的可定制模板，这使得能够使用高级综合工具生成具有高效资源利用率的低延迟FPGA设计。评估结果表明，我们的FPGA实现比GPU实现快9.0倍，功率效率高13.1倍。与以前的FPGA实现相比，这项工作实现了6.51至16.7倍的低延迟。此外，我们的FPGA设计的延迟足够低，可以在亚微秒实时碰撞机触发系统中部署GNN，使其能够从提高的准确性中受益。所提出的LL-GNN设计通过使复杂的算法能够有效地处理实验数据来推进下一代触发系统。
This work presents a novel reconfigurable architecture for Low Latency Graph Neural Network (LL-GNN) designs for particle detectors, delivering unprecedented low latency performance. Incorporating FPGA-based GNNs into particle detectors presents a unique challenge since it requires sub-microsecond latency to deploy the networks for online event selection with a data rate of hundreds of terabytes per second in the Level-1 triggers at the CERN Large Hadron Collider experiments. This article proposes a novel outer-product based matrix multiplication approach, which is enhanced by exploiting the structured adjacency matrix and a column-major data layout. In addition, we propose a custom code transformation for the matrix multiplication operations, which leverages the structured sparsity patterns and binary features of adjacency matrices to reduce latency and improve hardware efficiency. Moreover, a fusion step is introduced to further reduce the end-to-end design latency by eliminating unnecessary boundaries. Furthermore, a GNN-specific algorithm-hardware co-design approach is presented which not only finds a design with a much better latency but also finds a high accuracy design under given latency constraints. To facilitate this, a customizable template for this low latency GNN hardware architecture has been designed and open-sourced, which enables the generation of low-latency FPGA designs with efficient resource utilization using a high-level synthesis tool. Evaluation results show that our FPGA implementation is up to 9.0 times faster and achieves up to 13.1 times higher power efficiency than a GPU implementation. Compared to the previous FPGA implementations, this work achieves 6.51 to 16.7 times lower latency. Moreover, the latency of our FPGA design is sufficiently low to enable deployment of GNNs in a sub-microsecond, real-time collider trigger system, enabling it to benefit from improved accuracy. The proposed LL-GNN design advances the next generation of trigger systems by enabling sophisticated algorithms to process experimental data efficiently.