Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors
Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors
复制标题
飞法拉和亚飞法拉 MOM 电容器的匹配特性
DOI：
10.1109/tcsi.2016.2537824
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
K. Salama
中科院分区：
文献类型：
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作者：
H. Omran;H. Alahmadi;K. Salama
小型金属-氧化物-金属（Metal-Oxide-Metal，简称MOSFET）电容器是高能效混合信号集成电路设计的关键。然而，只有很少的报告讨论他们的匹配性能的基础上大量的测量数据集。在本文中，我们报告的匹配特性的毫微微法拉和亚毫微微法拉的垂直场平行板电容器和横向场边缘电容器。我们研究了指长和指间距对横向场电容失配的影响。此外，我们比较了垂直场和横向场电容的匹配特性和面积效率。我们使用直接失配测量技术，我们说明了它的可行性，通过实验测量和蒙特卡罗模拟。测试芯片采用0.18 μ mCMOS工艺制作。大量的测试结构的特点（4800测试结构），这提高了统计的可靠性提取的失配信息。尽管传统的智慧，广泛的测量表明，垂直场和横向场的电容器具有相同的匹配特性时，实际的电容器面积被认为是。测量表明，失配取决于电容器面积，但不取决于间距;因此，对于给定的失配规格，横向场双稳态电容器可以通过增加电容器指之间的间距来具有任意小的电容，以增加芯片面积为代价。
Small metal-oxide-metal (MOM) capacitors are essential to energy-efficient mixed-signal integrated circuit design. However, only few reports discuss their matching properties based on large sets of measured data. In this paper, we report matching properties of femtofarad and sub-femtofarad MOM vertical-field parallel-plate capacitors and lateral-field fringing capacitors. We study the effect of both the finger-length and finger-spacing on the mismatch of lateral-field capacitors. In addition, we compare the matching properties and the area efficiency of vertical-field and lateral-field capacitors. We use direct mismatch measurement technique, and we illustrate its feasibility using experimental measurements and Monte Carlo simulations. The test-chips are fabricated in a 0.18 μm CMOS process. A large number of test structures is characterized (4800 test structures), which improves the statistical reliability of the extracted mismatch information. Despite conventional wisdom, extensive measurements show that vertical-field and lateral-field MOM capacitors have the same matching properties when the actual capacitor area is considered. Measurements show that the mismatch depends on the capacitor area but not on the spacing; thus, for a given mismatch specification, the lateral-field MOM capacitor can have arbitrarily small capacitance by increasing the spacing between the capacitor fingers, at the expense of increased chip area.