Impact of SiGe layer thickness in starting substrates on strained Ge-on-insulator pMOSFETs fabricated by Ge condensation method
Impact of SiGe layer thickness in starting substrates on strained Ge-on-insulator pMOSFETs fabricated by Ge condensation method
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DOI：
10.1063/1.5068713
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发表时间：
2019-02
影响因子：
4
通讯作者：
K. Jo;Wu-Kang Kim;M. Takenaka;S. Takagi
中科院分区：
文献类型：
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作者：
K. Jo;Wu-Kang Kim;M. Takenaka;S. Takagi
我们研究了在Si/Si0.25Ge0.75/SOI（100）结构的初始衬底中，Ge的厚度对Ge-绝缘体（GOI）薄膜性能的影响。我们使用原子力显微镜和拉曼光谱评估的GOI薄膜的物理特性。结果表明，与60 nm厚的SiGe相比，40 nm厚的Si_（0.75）Ge_（0.25）通过缓慢冷却的Ge凝聚工艺可以得到10 nm厚的GOI薄膜，其压缩应变（ec = 1.75%）和空间应变分布更均匀.应变弛豫的这种抑制是由于较薄的SiGe层导致的较低的总应变能。通过使用这种GOI衬底，10 nm厚的GOI p沟道金属氧化物半导体场效应晶体管（pMOSFET）被证明具有μh = 467 cm 2 V−1 s−1和Ion/Ioff > 7.2 × 105的高性能。随着测量温度从298 K降低到100 K，10 nm厚GOI pMOSFET的有效空穴迁移率显著增加，研究了Si/Si0.25Ge0.75/SOI（100）结构中SiGe厚度对Ge凝聚过程中绝缘体上Ge（GOI）迁移率的影响。薄膜性能我们使用原子力显微镜和拉曼光谱评估的GOI薄膜的物理特性。结果表明，与60 nm厚的SiGe相比，40 nm厚的Si_（0.75）Ge_（0.25）通过缓慢冷却的Ge凝聚工艺可以得到10 nm厚的GOI薄膜，其压缩应变（ec = 1.75%）和空间应变分布更均匀.应变弛豫的这种抑制是由于较薄的SiGe层导致的较低的总应变能。通过使用这种GOI衬底，10 nm厚的GOI p沟道金属氧化物半导体场效应晶体管（pMOSFET）被证明具有μh = 467 cm 2 V−1 s−1和Ion/Ioff > 7.2 × 105的高性能。随着测量温度从298 K降低到100 K，10 nm厚的GOI pMOSFET的有效空穴迁移率显著增加，表明高贡献率。
We study the impact of the SiGe thickness in starting substrates composed of Si/Si0.25Ge0.75/SOI(100) structures for the Ge condensation process on the resulting Ge-on-insulator (GOI) film properties. We evaluate the physical properties of the GOI films using AFM and Raman spectroscopy. It is found that 10-nm-thick GOI films with higher compressive strain (ec = 1.75%) and more uniform spatial strain distribution are obtained for 40 nm-thick-Si0.75Ge0.25 through a Ge condensation process with slow cooling than 60 nm-thick-SiGe. This suppression of strain relaxation is due to the lower total strain energy by the thinner SiGe layer. By using this GOI substrate, 10-nm-thick GOI p-channel metal-oxide-semiconductor field effect transistors (pMOSFETs) are demonstrated with the high performance of μh = 467 cm2 V−1 s−1 and Ion/Ioff > 7.2 × 105. The effective hole mobility of the 10 nm-thick GOI pMOSFET increases significantly with reducing measurement temperature from 298 K to 100 K, indicating the high contribution of phonon scattering to the mobility.We study the impact of the SiGe thickness in starting substrates composed of Si/Si0.25Ge0.75/SOI(100) structures for the Ge condensation process on the resulting Ge-on-insulator (GOI) film properties. We evaluate the physical properties of the GOI films using AFM and Raman spectroscopy. It is found that 10-nm-thick GOI films with higher compressive strain (ec = 1.75%) and more uniform spatial strain distribution are obtained for 40 nm-thick-Si0.75Ge0.25 through a Ge condensation process with slow cooling than 60 nm-thick-SiGe. This suppression of strain relaxation is due to the lower total strain energy by the thinner SiGe layer. By using this GOI substrate, 10-nm-thick GOI p-channel metal-oxide-semiconductor field effect transistors (pMOSFETs) are demonstrated with the high performance of μh = 467 cm2 V−1 s−1 and Ion/Ioff > 7.2 × 105. The effective hole mobility of the 10 nm-thick GOI pMOSFET increases significantly with reducing measurement temperature from 298 K to 100 K, indicating the high contributi...