Design of a high-throughput low-power IS95 Viterbi decoder
Design of a high-throughput low-power IS95 Viterbi decoder
复制标题
高通量低功耗IS95维特比译码器的设计
DOI：
10.1145/513918.513988
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发表时间：
2002
期刊：
影响因子：
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通讯作者：
M. Papaefthymiou
中科院分区：
文献类型：
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作者：
Xun Liu;M. Papaefthymiou
高吞吐量大状态维特比译码器的设计依赖于多个算术单元的使用。这些并行处理器之间的全局通信通道通常由长互连线组成，导致大面积和高功耗。在本文中，我们提出了一个面向数据传输的设计方法来实现一个低功耗的256状态速率1/3 IS 95维特比解码器。我们的架构级方案使用操作分区，包装，和调度，以分析和优化互连的影响，在早期设计阶段。与其他已发表的Viterbi解码器相比，我们的方法减少了高达75%的全球数据传输，并减少了高达48%的全球总线的数量，同时使深度流水线的数据路径的使用没有数据转发。在各个处理器的RTL实现中，我们将预计算与饱和算法相结合，以进一步降低功耗，并证明不会降低编码性能。使用0.25 /spl mu/m标准单元库设计，我们的解码器实现了20 Mbps的吞吐量在模拟和耗散只有450 mW。
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data-transfer oriented design methodology to implement a low-power 256-state rate-1/3 IS95 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the RTL implementation of the individual processors, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 /spl mu/m standard cell library, our decoder achieves a throughput of 20 Mbps in simulation and dissipates only 450 mW.