A high-precision time-to-digital converter using a two-level conversion scheme
A high-precision time-to-digital converter using a two-level conversion scheme
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一种采用两级转换方案的高精度时间数字转换器
DOI：
10.1109/tns.2004.832902
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
H. Tsao
中科院分区：
文献类型：
--
作者：
Chorng;Poki Chen;H. Tsao
本文描述了一种采用两电平转换方案的时间-数字转换器(TDC)的设计。第一级由延迟锁定环(DLL)辅助的多相采样技术完成。然后，对输入信号及其相邻的采样时钟进行处理，并将其送入游标延迟线(VDL)采样电路。与具有相同动态范围的单电平VDL采样电路相比，所提出的TDC能够以较少的硬件提供精确的分辨率。提出了一种新的双DLL电路结构，以稳定延迟控制，使其不受工艺和环境变化的影响。测试芯片采用0.35/SPL Mu/m数字工艺设计和制作。在输入参考时钟为160 MHz的情况下，TDC的分辨率达到24ps。DNL小于/SPL+MN/0.55LSB，INL在+1LSB/SPL sim/-1.5LSB范围内。
This paper describes a design of time-to-digital converter (TDC) utilising a two-level conversion scheme. The first level is accomplished by a multi-phase sampling technique with the aid of delay-locked loop (DLL). Then the input signal and its adjacent sampling clock are manipulated and sent into a vernier delay line (VDL) sampling circuit. The proposed TDC can provide precise resolution with less hardware comparing to one level VDL sampling circuit possessing the same dynamic range. A new architecture of dual DLL circuit is also introduced to stabilize delay control against process and ambient variation. The test chip is designed and fabricated in 0.35/spl mu/m digital process. With an input reference clock at 160MHz, the TDC achieves 24ps resolution. The DNL is less than /spl plusmn/0.55LSB and INL within +1LSB/spl sim/-1.5LSB.