Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs
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DOI：
10.1109/iscas.2019.8702386
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Jinghao Ye;N. Togawa;M. Yanagisawa;Youhua Shi
中科院分区：
文献类型：
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作者：
Jinghao Ye;N. Togawa;M. Yanagisawa;Youhua Shi
本文将忠实截断加法器用于低成本的FIR实现，改进了现有的基于CSD的FIR滤波器设计，在满足精度要求的前提下进一步减小了面积和功耗。为了解决截断加法器带来的精度损失，本文对截断加法器进行了静态误差分析。此外，基于我们的数学分析，我们证明了在给定精度约束的情况下，可以毫不费力地确定最优的截断加法器结构，以实现面积功耗高效的FIR设计。对不同FIR设计的评估结果表明，在平均误差为1ulp的情况下，所提出的最优截断加法器设计可以实现16.8%的∼面积减少35.4%的面积和11.8%的∼27.9%的功耗节约。
Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8%∼35.4% reduction in area and 11.8%∼27.9% in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.