Fast ReRoute on Programmable Switches
Fast ReRoute on Programmable Switches
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DOI：
10.1109/tnet.2020.3045293
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发表时间：
2021-04-01
影响因子：
3.7
通讯作者：
Schmid, Stefan
中科院分区：
文献类型：
--
作者：
Chiesa, Marco;Sedar, Roshan;Schmid, Stefan
高度可靠的通信网络通常依赖于某种快速重路由（FRR）机制，该机制允许在故障时完全在数据平面中快速重路由流量。本文研究了新兴的可重构开关的FRR机制的设计。我们的主要贡献是一个FRR原语的可编程数据平面，PURR，它提供了低故障转移延迟和高交换吞吐量，避免数据包再循环。PURR容忍多个并发故障，并具有最小的内存需求，确保紧凑的转发表，通过揭示一个有趣的连接到经典的“字符串理论”（即，stringology），特别是最短公共超序列问题。PURR非常适合于高速匹配动作转发架构（例如，比萨），并支持各种FRR机制的实施。我们的模拟和原型实现（在FPGA和Tofino交换机上）表明，与实现最先进的FRR机制时的朴素编码相比，PURR将TCAM内存占用率提高了1.5倍至10.8倍。与基于再循环数据包的方法相比，PURR还将数据中心流量的延迟和吞吐量分别提高了2.8倍至5.5倍和1.2倍至2倍。
Highly dependable communication networks usually rely on some kind of Fast Re-Route (FRR) mechanism which allows to quickly re-route traffic upon failures, entirely in the data plane. This paper studies the design of FRR mechanisms for emerging reconfigurable switches. Our main contribution is an FRR primitive for programmable data planes, PURR, which provides low failover latency and high switch throughput, by avoiding packet recirculation. PURR tolerates multiple concurrent failures and comes with minimal memory requirements, ensuring compact forwarding tables, by unveiling an intriguing connection to classic "string theory" (i.e., stringology), and in particular, the shortest common supersequence problem. PURR is well-suited for high-speed match-action forwarding architectures (e.g., PISA) and supports the implementation of a broad variety of FRR mechanisms. Our simulations and prototype implementation (on an FPGA and a Tofino switch) show that PURR improves TCAM memory occupancy by a factor of 1.5x-10.8x compared to a naive encoding when implementing state-of-the-art FRR mechanisms. PURR also improves the latency and throughput of datacenter traffic up to a factor of 2.8x-5.5x and 1.2x-2x, respectively, compared to approaches based on recirculating packets.