The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes
The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes
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DOI：
10.1109/irps.2012.6241839
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发表时间：
2012-04
期刊：
影响因子：
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通讯作者：
B. Kaczer;Jacopo Franco;M. Toledano-Luque;Philippe Roussel;M. Bukhori;A. Asenov;B. Schwarz;M. Bina;Tibor Grasser;Guido Groeseneken
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文献类型：
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作者：
B. Kaczer;Jacopo Franco;M. Toledano-Luque;Philippe Roussel;M. Bukhori;A. Asenov;B. Schwarz;M. Bina;Tibor Grasser;Guido Groeseneken
在只有少数栅极氧化物缺陷的纳米尺寸的FET器件中，通常测量的阈值电压偏移与高栅极偏置下的器件行为没有明显的相关性。在捕获单个载流子之后在阈值电压处观察到的最大偏移在较高的栅极偏置下减小。这种降低效应进一步显示出在较低的沟道掺杂被放大。从3D数值模拟获得的理解捕获在一个简单的分析描述的单个陷阱电荷的FET特性的影响，在整个栅极偏置范围。潜在的使用说明在改进的寿命预测和电路模拟的时间依赖性的变化。
In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold voltage after the capture of a single carrier are reduced at higher gate biases. This degradation-mitigating effect is further shown to be amplified at lower channel doping. The understanding gained from 3D numerical simulations is captured in a simple analytic description of a single trapped-charge impact on the FET characteristics in the entire gate bias range. Potential use is illustrated in an improved lifetime projection and in circuit simulations of time-dependent variability.