64-point fast efficient FFT architecture using Radix-23 single path delay feedback
64-point fast efficient FFT architecture using Radix-23 single path delay feedback
复制标题
使用 Radix-23 单路径延迟反馈的 64 点快速高效 FFT 架构
DOI：
10.1109/iceei.2009.5254734
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发表时间：
2009
期刊：
影响因子：
--
通讯作者：
Ade Irawan
中科院分区：
文献类型：
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作者：
T. Adiono;M. S. Irsyadi;Yan Syafri Hidayat;Ade Irawan
本文提出了一种新的64点快速傅里叶变换电路的设计。该设计基于基-23算法，采用单路延迟反馈结构实现。这种方法确保了高内存和乘法器利用率。64点FFT通过分解成8点FFT的二维结构来实现。每个FFT被重新分解为4点和2点FFT。这种分解将非平凡旋转因子的数量减少到仅仅一个。因此，我们只需要一个复杂的乘法器的设计。复数乘法器采用改进的Booth（基-4）编码算法实现，提高了运算速度.通过功能仿真、时序仿真和FPGA实现，验证了该电路的有效性和高效性。所提出的设计已成功地综合使用Synopsys与台积电0.18µ技术。核心面积为0.47 mm 2。功耗为29.7 mW。时间延迟为6 ns。该电路在116个时钟周期内计算一个串行到串行数据。因此，我们的设计有3个优点：小面积，低功耗，快速计算。
Here we present a new design of a 64-point Fast Fourier Transform circuit. The design is derived from Radix-23 algorithm and implemented using Single Path Delay Feedback architecture. This approach ensures high memory and multiplier utilizations. The 64-Point FFT is realized by decomposing into two-dimensional structure of 8-point FFTs. Each of this FFT is re-decomposed into 4-point and 2-point FFTs. This decomposition reduces the number of non-trivial twiddle factor into just one. Thus we only need one complex multiplier for the design. The complex multiplier is realized using modified Booth (radix-4) encoding algorithm to achieve faster computational speed. The validity and efficiency of the proposed circuit has been thoroughly verified by functional simulation, timing simulation, and FPGA implementation. The proposed design has been successfully synthesized using Synopsys with TSMC 0.18µ technology. The core area is 0.47 mm2. The power consumption is 29.7 mW. The time delay is 6 ns. The circuit computes one serial-to-serial data in 116 clock cycles. Thus our design has 3 advantages: small area, low power consumption, and fast computation.