Modeling of Stacking Fault Expansion Velocity of Body Diode in 4H-SiC MOSFET
Modeling of Stacking Fault Expansion Velocity of Body Diode in 4H-SiC MOSFET
复制标题
4H-SiC MOSFET 中体二极管的堆垛层错扩展速度建模
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
Y. Shimamoto
中科院分区：
文献类型：
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作者：
K. Konishi;Ryusei Fujita;A. Shima;Y. Shimamoto
提出了一个模型来解释4 H-SiC MOSFET体二极管的正向电压退化，并评估SF膨胀的速度。首先，通过原位光致发光（PL）观察，我们研究了层错（SF）如何从4 H-SiC外延层中的基面位错（BPD）扩展。其次，研制了双扩散MOSFET，并在退化前后进行了测量。然后，采用PL成像和电学测量相结合的方法对薄膜的正向电压退化特性进行了建模，计算结果与实测结果吻合较好。最后，我们测试了SiC MOSFET在各种应力条件下的SF膨胀速度，并通过计算评估。这一结果表明，SF膨胀的速度随着正向电流密度和结温的增加而增加。
We present a model to explain forward voltage degradation of body diode in 4H-SiC MOSFET, and evaluate the velocity of SF expansion. First, by using in-situ photoluminescence (PL) observation, we investigated how a stacking fault (SF) expands from a basal plane dislocations (BPD) in the 4H-SiC epitaxial layer. Second, double-diffused MOSFETs were developed and measured before and after degradation. Then, the characteristics of the forward voltage degradation were modeled by a combination of PL imaging and electrical measurement, and the calculated characteristics are in good agreement with the measured ones. Finally, we tested the SiC MOSFETs under various stress conditions and evaluated the velocity of the SF expansion by calculation. This results indicate that the velocity of SF expansion increased with increasing forward current density and junction temperature.