Modeling Simplification for Thermal Mechanical Analysis of High Density Chip-to-Substrate Connections
Modeling Simplification for Thermal Mechanical Analysis of High Density Chip-to-Substrate Connections
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DOI：
10.1115/1.4005289
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发表时间：
2011-12
影响因子：
1.6
通讯作者：
P. An;P. Kohl
中科院分区：
文献类型：
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作者：
P. An;P. Kohl
有限元建模（FEM）是设计可靠的芯片-衬底连接的重要组成部分。然而，随着输入/输出连接数量的增加，FEM可能很快变得复杂。三维（3D）芯片-衬底模型通常被简化，其中仅考虑芯片-衬底结构的部分，以便节省计算机资源和时间。芯片对称性通常用于将模型从全芯片结构简化为四分之一或八分之一模型。最近，一个更简单的3D模型，一般平面变形（GPD）切片模型，已被用来表征的结构上的全芯片和局部区域的属性，如在结构的焊球疲劳。在这项研究中，GPD模型的准确性进行检查，通过比较倒装芯片，铜柱封装从各种完整和部分芯片模型的GDP模型的机械行为。此外，通过在切片中间引入对称面和选择适当的边界条件，可以将GPD模型进一步简化为半GPD模型。比较了每个模型所需的节点数和不同有限元模型的精度。对硅片最大应力的分析表明，全芯片模型、四分之一模型和八分之一模型都收敛到相同的结果。然而，GPD和半GPD模型，与以前使用的边界条件，收敛到一个不同的应力值从全芯片模型。与更完整的全芯片FEM模型相比，小型36 I/O封装的GPD模型的误差为4.7%。与全芯片模型相比，GPD模型中的位移误差超过50%，并且随着结构的增大而增大。GPD模型的高位移误差是由于通常使用的边界条件忽略了相邻I/O对GPD切片侧壁的影响。提出了一个优化方程来解释GPD侧壁上的应力的空间变化。对于36柱阵列，GPD位移误差从50%减小到3.3%。[DOI电话：10.1115/1.4005289
Finite element modeling (FEM) is an important component in the design of reliable chipto-substrate connections. However, FEM can quickly become complex as the number of input/output connections increases. Three-dimensional (3D) chip-substrate models are usually simplified where only portions of the chip-substrate structure is considered in order to conserve computer resources and time. Chip symmetry is often used to simplify the models from full-chip structures to quarter or octant models. Recently, an even simpler 3D model, general plane deformation (GPD) slice model, has been used to characterize the properties of the full-chip and local regions on the structures, such as in the structures for solder ball fatigue. In this study, the accuracy of the GPD model is examined by comparing the mechanical behavior of a flip-chip, copper pillar package from various full and partial chip models to that of the GDP model. In addition, it is shown that the GPD model can be further simplified to a half-GPD model by using the symmetry plane in the middle of the slice and choosing the proper boundary conditions. The number of nodes required for each model and the accuracy of the different FEM models are compared. Analysis of the maximum stress in the silicon chip shows that the full-chip model, quarter model, and octant model all convergence to the same result. However, the GPD and half-GPD models, with the previously used boundary conditions, converge to a different stress values from that of the full-chip models. The error in the GPD models for small, 36 I/O package was 4.7% compared to the more complete, full-chip FEM models. The displacement error in the GPD models was more than 50%, compared to the full-chip models, and increased with larger structures. The high displacement error of the GPD models was due to the ordinarily used boundary conditions which neglect the effect from adjacent I/O on the sidewall of the GPD slice. An optimization equation is proposed to account for the spatial variation in the stress on the GPD sidewall. The GPD displacement error was reduced from 50% to 3.3% for the 36 pillar array. [DOI: 10.1115/1.4005289]