The Flexible Processor-dynamically reconfigurable logic array for personal-use emulation system
The Flexible Processor-dynamically reconfigurable logic array for personal-use emulation system
复制标题
用于个人使用仿真系统的灵活处理器动态可重构逻辑阵列
DOI：
10.1109/vlsic.2003.1221226
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
T. Ohmi
中科院分区：
文献类型：
--
作者：
T. Ohkawa;T. Nozawa;M. Fujibayashi;N. Miyamoto;K. Leo;S. Kita;K. Kotani;T. Ohmi
开发了一种适用于单芯片仿真系统的动态可重构逻辑阵列--柔性处理器。它演示了通过新开发的时间通信模块(TCM)从原始电路中分离出来的子电路的顺序执行。为了提高仿真速度，实现了一个逻辑单元，与传统的查找表相比，可以减少30%的配置数据。该芯片(3.9/spl次/3.9 mm/sup 2/)采用0.6/splµ/m工艺制作，工作频率为33 MHz，电源电压为5.0V。
A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration data by 30% as compared to conventional Look-Up-Table, is implemented. The chip (3.9/spl times/3.9 mm/sup 2/) fabricated with 0.6 /spl mu/m CMOS technology operates at 33 MHz with 5.0 V power supply.