Superpipelined high-performance optical-flow computation architecture
Superpipelined high-performance optical-flow computation architecture
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DOI：
10.1016/j.cviu.2008.05.006
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发表时间：
2008-12-01
影响因子：
4.5
通讯作者：
Luis Bernier, Jose
中科院分区：
文献类型：
--
作者：
Diaz, Javier;Ros, Eduardo;Luis Bernier, Jose
光流计算是一种众所周知的技术，并且在一些重要领域中，这种视觉模态的应用引起了人们的高度兴趣。然而，大多数现实世界的应用程序需要实时处理。所有这些问题最近才得到解决。迄今为止描述的大多数实时系统使用的基本模型限制了它们对通用任务的适用性，特别是当呈现快速运动或需要子像素运动分辨率时。因此，而不是实现一个复杂的光流的方法，我们在这里描述一个非常高的帧速率光流处理系统。图像传感器技术的最新进展使得现在可以使用高帧速率传感器来正确地采样快速运动（即，作为低运动场景），这使得基于梯度的方法在任何实时实现的准确性和资源消耗方面成为最佳选择之一。利用这种算法的规则数据，我们的方法实现了一种新的超流水线。全并行架构的光流处理。该系统完全工作，并组织成70多个流水线阶段，实现了每个时钟周期一个像素的数据吞吐量。这种计算方案非常适合于FPGA技术和VLSI实现。开发的定制DSP架构能够处理高达每秒170帧的分辨率为800 - 600像素。我们讨论了高帧罕见处理的优点，并证明选择的实施光流模型。我们分析了这种架构，测量系统的资源需求，使用FPGA器件，最后评估系统的性能，并将其与文献中描述的其他方法进行比较。(c)2008年爱思唯尔公司All rights reserved.
Optical-flow computation is a well-known technique and there are important fields in which the application of this visual modality commands high interest. Nevertheless, most real-world applications require real-time processing. all issue which has only recently been addressed. Most real-time systems described to date use basic models which limit their applicability to generic tasks, especially when fast motion is presented or when subpixel motion resolution is required. Therefore, instead of implementing a complex optical-flow approach, we describe here a very high-frame-rate optical-flow processing system. Recent advances in image sensor technology make it possible nowadays to use high-frame-rate sensors, to properly sample fast motion (i.e. as a low-motion scene), which makes a gradient-based approach one of the best options in terms Of accuracy and comsumption of resources for any real-time implementation. Taking advantage of the regular data now of this kind of algorithm, our approach implements a novel superpipelined. fully parallelized architecture for optical-flow processing. The system is fully working and is organized into More than 70 pipeline stages, which achieve a data throughput of one pixel per clock cycle. This computing scheme is well suited to FPGA technology and VLSI implementation. The developed Customized DSP architecture is capable of processing up to 170 frames per second at a resolution of 800 600 pixels. We discuss the advantages of high-frame-rare processing and justify the optical-flow model chosen for the implementation. We analyze this architecture, measure the system resource requrements Using FPGA devices and finally evaluate the system's performance and compare it with other approaches described in the literature. (c) 2008 Elsevier Inc. All rights reserved.