Scan test data volume reduction in multi-clocked designs with safe capture technique
Scan test data volume reduction in multi-clocked designs with safe capture technique
复制标题
通过安全捕获技术减少多时钟设计中的扫描测试数据量
DOI：
10.1109/test.2002.1041755
复制
发表时间：
2002
期刊：
影响因子：
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通讯作者：
J. Waicukauski
中科院分区：
文献类型：
--
作者：
V. Jain;J. Waicukauski
随着设计规模和复杂度的不断增加，多时钟域设计风格已成为业界的新趋势。测试具有多个时钟的电路的几种技术是已知的;然而，对于大型和复杂的电路，它们经常导致增加的测试时间和测试器存储器。本文提出了一种策略，以减少在ATPG的测试模式计数，强制一个安全的捕获行为时，在捕获过程中应用多个时钟。多个时钟的使用允许额外的可观测性，这可以显著减少具有许多时钟的电路的模式计数。实验结果表明，该策略的结果在更大的，而且，更一致的减少测试大小。
As a result of increasing design size and complexity, the multiple clock domain design style has become a new trend in the industry. Several techniques to test circuits with multiple clocks are known; however, they often result in increased test time and tester memory for large and complex circuits. This paper presents a strategy to reduce the test pattern count during ATPG by forcing a safe capture behavior when multiple clocks are applied during capture. The usage of multiple clocks allows additional observability, which can significantly reduce the pattern count for circuits with many clocks. Experimental results indicate that proposed strategy results in larger and moreover, more consistent reduction in test sizes.