Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance
Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance
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DOI：
10.1109/tns.2014.2349504
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发表时间：
2014-09
影响因子：
1.8
通讯作者：
S. Jeon;Soonyoung Lee;S. Baeg;Ilgon Kim;Gunrae Kim
中科院分区：
文献类型：
--
作者：
S. Jeon;Soonyoung Lee;S. Baeg;Ilgon Kim;Gunrae Kim
本文探讨了错误检测方案的有效性，越来越多的单元翻转占主导地位的技术，特别是SRAM。审查交织距离，奇偶校验码，以及抽头进行检查每个属性。在此基础上，提出了一种新的差错检测方案，该方案综合利用了阱抽头的多信元翻转抑制效应、奇偶校验码的可检测性和交织距离方案，从而形成了一种既灵活又具有较高实现前景的有效差错检测方案。一个行深度模型被创建来评估所提出的方案的有效性。该模型表明，具有更大的多单元翻转尺寸和比率的先进技术将经历错误检测失败的方案，如单错误校正-双错误检测，而所提出的方案仍然有效。实验数据支持这样的前提，即井抽头抑制多个单元翻转，因为发现1%的交叉井抽头。所提出的方案被认为是至少三倍更好地防止错误检测故障比单纠错双错误检测。
This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducted to examine each attribute. Then, the paper proposes a novel error detection scheme with the harmonious use of the multiple-cell upset inhibition effects of well-taps, the detectability of parity codes, and an interleaving distance scheme to create an effective error detection scheme that is both flexible and has a high implementation prospect. A row depth model is created to assess the effectiveness of the proposed scheme. The model shows that advanced technologies with greater multiple-cell upset sizes and ratios will experience error detection failures with schemes such as single error correction-double error detection, whereas the proposed scheme remains effective. Experimental data supports the premise that well-taps inhibit multiple-cell upset, as it is found that 1% cross well-taps. The proposed scheme is recognized to be at least three times better against error detection failures than single error correction-double error detection.