Implication graph based domino logic synthesis
Implication graph based domino logic synthesis
复制标题
基于蕴涵图的多米诺逻辑综合
DOI：
10.1109/iccad.1999.810632
复制
发表时间：
1999
期刊：
影响因子：
--
通讯作者：
S. Kang
中科院分区：
文献类型：
--
作者：
Ki;C. Liu;S. Kang
在本文中，我们提出了一种新的方法来解决多米诺逻辑综合中消除逆变器的问题。将一小部分静态CMOS逻辑引入了电路，以避免复制导致重大面积罚款。为了最大化多米诺骨牌逻辑部分并最大程度地减少静态CMOS逻辑部分，提出了基于ATPG的广义逻辑转换，以消除或重新安置目标逆变器。基于主要的强制性分配集合（DSMA）和相应的含义图的新概念，我们提出了算法，以确定目标逆变器的最小候选候选者。实验结果表明，基于暗示图的逻辑转换可以将晶体管计数降低25％，而功率延迟产物平均减少25％。
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on an implication graph can reduce transistor counts by 25% and power delay product by 25% on average.