An efficient approach to constrained via minimization for two-layer VLSI routing
An efficient approach to constrained via minimization for two-layer VLSI routing
复制标题
一种有效的两层 VLSI 布线约束通孔最小化方法
DOI：
10.1109/aspdac.1999.759982
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
H. Cheung
中科院分区：
文献类型：
--
作者：
Maolin Tang;K. Eshraghian;H. Cheung
约束过孔最小化是指在超大规模集成电路布线中重新分配布线线段，以使过孔数量最小化的问题。本文提出了一种新的双层VLSI布线方法。这种方法能够处理任何类型的布线，并允许在候选通孔处分割任意数量的导线段。
Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.