Slew-aware clock tree design for reliable subthreshold circuits
Slew-aware clock tree design for reliable subthreshold circuits
复制标题
用于可靠亚阈值电路的转换感知时钟树设计
DOI：
10.1145/1594233.1594239
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
S. Mukhopadhyay
中科院分区：
文献类型：
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作者：
Jeremy R. Tolbert;Xin Zhao;S. Lim;S. Mukhopadhyay
本文分析了亚阈值电路中时钟摆幅的影响。具体来说，我们解决的问题，在寄存器控制时钟摆率的变化可能会导致严重的时序违规。我们发现，时钟摆率的变化可能会导致锁存器的定时指标，如建立，保持和时钟到Q时间偏离90%的设计目标。基于这些观察，我们认识到时钟摆率控制在亚阈值电路中的重要性。我们提出了一个系统的方法来设计亚阈值电路的时钟树，以减少时钟摆率的变化，同时最大限度地减少功耗树。我们发现，一个更严格的节点电容控制是必要的，以控制在亚阈值时钟树，这可能会增加功耗的摆率。认识到线电阻在亚阈值电路中的影响可以忽略不计，我们表明适当的导线尺寸是必要的，以减少时钟功率。最后，我们提出了一个动态的节点电容控制技术，允许更大的摆在较早的网络的树，同时控制它更积极地接近汇节点。结合的方法，包括线尺寸和动态节点电容控制，可以实现更好的压摆控制（和更好的时序控制）在亚阈值电路在较低的功率。
In the paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause latch timing metrics such as setup, hold and clock-to-q times to deviate by 90% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the power dissipation in the tree. We show that a tighter nodal capacitance control is necessary to control the slew in a subthreshold clock tree, which can increase the power dissipation. Recognizing that the wire resistances have a negligible effect in subthreshold circuits, we show proper wire sizing is necessary to reduce the clock power. Finally, we propose a dynamic nodal capacitance control technique that allows larger slew at the earlier nets of the tree while controlling it more aggressively near the sink nodes. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower power in subthreshold circuits.