A 10,000 Frames/s 0.18 μm CMOS Digital Pixel Sensor with Pixel-Level Memory
A 10,000 Frames/s 0.18 μm CMOS Digital Pixel Sensor with Pixel-Level Memory
复制标题
具有像素级存储器的 10,000 帧/秒 0.18 μm CMOS 数字像素传感器
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
A. Gamal
中科院分区：
文献类型：
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作者：
S. Kleinfelder;Sukhwan Lim;Xinqiao Liu;A. Gamal
在数字像素传感器（DPS）中，每个像素都有一个ADC，所有ADC并行工作，并且数字数据直接从图像传感器阵列中读取，就像传统的数字存储器一样[1]。与模拟图像传感器相比，DPS架构具有多个优势，包括通过CMOS技术实现更好的缩放，这是由于降低了模拟电路性能要求，并消除了列固定模式噪声和列读出噪声。利用每个像素的ADC，大规模并行转换和高速数字读出成为可能，完全消除了模拟读出瓶颈。这有利于传统的高速成像应用，并实现新的成像增强功能，例如用于增加传感器动态范围的多采样[2]。然而，使用DPS实现可接受的像素尺寸需要使用0.18 μm或更低的CMOS工艺，由于电源电压降低和漏电流增加，这具有挑战性[3]。
In a Digital Pixel Sensor (DPS), each pixel has an ADC, all ADCs operate in parallel, and digital data is directly read out of the image sensor array as in a conventional digital memory [1]. The DPS architecture offers several advantages over analog image sensors including better scaling with CMOS technology due to reduced analog circuit performance demands and the elimination of column fixed-pattern noise and column readout noise. With an ADC per pixel, massively parallel conversion and high-speed digital readout become possible, completely eliminating analog readout bottlenecks. This benefits traditional high speed imaging applications and enables new imaging enhancement capabilities such as multiple sampling for increasing sensor dynamic range [2]. Achieving acceptable pixel sizes using DPS, however, requires the use of a 0.18 μm or below CMOS process, which is challenging due to reduced supply voltages and increased leakage currents [3].