An Eight-Channel 4.5-ps Precision Timestamps-Based Time Interval Counter in FPGA Chip
An Eight-Channel 4.5-ps Precision Timestamps-Based Time Interval Counter in FPGA Chip
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DOI：
10.1109/tim.2016.2564038
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发表时间：
2016-09-01
影响因子：
5.6
通讯作者：
Rozyc, Krzysztof
中科院分区：
文献类型：
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作者：
Szplet, Ryszard;Kwiatkowski, Pawel;Rozyc, Krzysztof
我们介绍了一种新型集成时间间隔（TI）计数器的设计、运行和测试结果，该计数器具有高分辨率（1.9 ps）、低测量不确定度（在高级测量模式下低于4.5 ps rms）和宽测量范围（超过1小时，易于扩展）。作为计数器的基础，TI测量可在8个独立通道中同时执行，而输入通道的高级配置可提高精度（高达3 ps）或测量速度（高达91.2 x 10(6)个注册事件/s）。基于时间戳（TS）原理实现了功能灵活性和高速度，这使得在计数器输入处出现的公共时间尺度上注册事件成为可能，然后测量任何注册事件之间的时间间隔。采用两级内插，第一级内插采用八相时钟，第二级内插采用等效时间编码延迟线，从而获得了较高的精度。时间计数器集成在一个单一的，具有成本效益的现场可编程门阵列芯片制造的28纳米CMOS工艺。
We present the design, operation, and test results of a new integrated time interval (TI) counter that provides high resolution (1.9 ps), low measurement uncertainty (below 4.5-ps rms in advanced measurement modes), and wide measurement range (above 1 h, easily extendable). Fundamental for the counter, TI measurements are simultaneously performed in eight independent channels, while the advanced configuration of input channels improves either the precision (up to 3 ps) or the measurement speed (up to 91.2 x 10(6) registered events/s). The functional flexibility and high speed are achieved based on the timestamp (TS) principle that makes possible registering on the common time scale events appearing at counter inputs and then measuring the time intervals between any registered events. The high precision is obtained by employing two-stage inner interpolation with an eight-phase clock in the first stage of interpolation and an equivalent time coding delay line in the second one. The time counter is integrated in a single, cost-effective field programmable gate array chip manufactured in a 28-nm CMOS process.