Low-power high-level synthesis using latches
Low-power high-level synthesis using latches
复制标题
使用锁存器的低功耗高级综合
DOI：
10.1109/aspdac.2001.913351
复制
发表时间：
2001
期刊：
影响因子：
--
通讯作者：
C. Kyung
中科院分区：
文献类型：
--
作者：
Woo;I. Park;C. Kyung
利用锁存器进行高阶合成在功率、面积甚至速度上都有许多优点。但是锁存器不能同时读写，而且通常需要两相非重叠坞，这对于短期设计来说是不愉快的选择。在本文中，我们提出了一种存储分配方法，使得在单时钟方案中使用锁存器作为存储元件成为可能。该方法对变量的生命周期稍加修改，可以适用于任何高级综合系统。实验结果表明，与使用时钟门控的传统电源管理方案相比，在几乎相同的面积内，功耗降低了39-65%。
High-level synthesis using latches has many merits in power, area and even in speed. But latches cannot be read and written at the same time and usually requires two-phase non-overlapping dock that is unpleasant choice for short-term design. In this paper we propose a storage allocation method that makes it possible to use latches as storage elements in single clocking scheme. The proposed method modifies the lifetime of variables slightly so that it can be applied to any high-level synthesis systems with small modification. The experimental results show 39-65% reduction in power consumption within almost the same area compared to the conventional power management scheme using clock gating.