Point-to-point connectivity between neuromorphic chips using address events
Point-to-point connectivity between neuromorphic chips using address events
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DOI：
10.1109/82.842110
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发表时间：
2000-05-01
影响因子：
4.4
通讯作者：
Boahen, KA
中科院分区：
文献类型：
--
作者：
Boahen, KA
本文讨论了神经形态芯片之间的连通性，利用定高定宽脉冲的定时来编码信息。地址事件(唯一标识N个神经元中的一个的log（2) (N)位数据包）用于在随机访问的时间复用通信信道上实时传输这些脉冲。本文量化了在分配带宽、授予访问权限和排队以及吞吐量要求方面的权衡，并得出结论，仲裁通道设计是最佳选择。在向读者介绍了这种自上而下的合成技术之后，仲裁通道采用异步数字VLSI CMOS系统的正式设计方法实现。随着三代设计的演变，它被显示。如何通过将神经元组织成行和列来减少仲裁、编码和解码的开销（从N到根号N），并通过利用局部性来减少时间(从log(2)(N)到2)；在仲裁器树和行-列架构中，以及集群活动中。吞吐量通过流水线和并行读取峰值来提高。描述了在这些混合模拟数字系统中减少串扰的简单技术。
This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log(2) (N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles-spikes clustered in space and in time, This paper quantifies tradeoffs heed in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice. The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown. how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to root N) by organizing neurons into rows and columns, and reduced in time (from log(2)(N) to 2) by exploiting locality; in the arbiter tree and in the row-column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog-digital systems are described.