The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project
The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project
复制标题
用于可插入 B 层项目的 FE-I4 像素读出片上系统重新提交
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
D. Arutinov
中科院分区：
文献类型：
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作者：
V. Zivkovic;J. Schipper;M. Garcia;A. Mekkaoui;M. Barbero;G. Darbo;D. Gnani;T. Hemperek;M. Menouni;D. Fougeron;F. Gensolen;F. Jensen;L. Caminada;V. Gromov;R. Kluit;J. Fleury;H. Krüger;M. Backhaus;X. Fang;L. Gonella;A. Rozanov;D. Arutinov
FE-I4是一种新的像素读数集成电路，旨在满足Atlas实验升级的要求。 FE-I4工程运行（称为FE-I4A）的第一批样本在要求的表演方面提供了有希望的结果。 FE-I4团队设想在实际的剥削之前进行了许多修改和微调，并计划在Atlas的可插入B层（IBL）内。随着IBL时间表大大推动，必须为FE-I4重新设计制定一个快速有效的计划。本文将介绍重新提交的主要目标，以及重新设计的主要变化，这是重新设计的驱动因素。此外，还将解决FE-I4的顶级验证和测试工作。
The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.