Power analysis of multiplier blocks
Power analysis of multiplier blocks
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DOI：
10.1109/iscas.2002.1009836
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发表时间：
2002-08
期刊：
影响因子：
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通讯作者：
S. Demirsoy;A. Dempster;I. Kale
中科院分区：
文献类型：
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作者：
S. Demirsoy;A. Dempster;I. Kale
在这项研究中，三个乘法器块产生不同的算法进行了分析，他们的功耗通过转换计数的基础上实现的Xilinx Virtex设备。对用于估计加法器输出端跳变相对数的高级Glitch-Path方法进行了改进，使其估计更精确，并提出了一种新的方法GP Score。几个设计问题进行了讨论，减少过渡的方式。
In this study, three multiplier-blocks generated by different algorithms are analyzed for their power consumption via transition count based on their implementation on the Xilinx Virtex device. The high level Glitch-Path method, which is used for estimating the relative figures of transitions occurring at the outputs of the adders, has been refined for more accurate estimation and a new method GP Score is proposed. Several design issues are discussed regarding ways of reducing the transitions.