Designing a practical data filter cache to improve both energy efficiency and performance
Designing a practical data filter cache to improve both energy efficiency and performance
复制标题
设计实用的数据过滤器缓存以提高能源效率和性能
DOI：
10.1145/2541228.2555310
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
P. Larsson
中科院分区：
文献类型：
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作者：
Alen Bardizbanyan;Magnus Själander;D. Whalley;P. Larsson
传统的数据过滤缓存（DFC）设计提高了处理器的能效，但降低了性能。此外，在先前的研究中建议的单周期线传输对一级数据缓存（L1 DC）面积和能量效率产生不利影响。我们提出了一个实用的DFC，在管道的早期访问，并在多个周期传输一行。我们的DFC设计提高了性能，并消除了加载的L1 DC访问，存储的L1 DC标记检查，以及加载和存储的数据转换后备缓冲区访问的很大一部分。我们的评估表明，建议的DFC可以减少42.5%的数据访问能量和提高4.2%的执行时间。
Conventional Data Filter Cache (DFC) designs improve processor energy efficiency, but degrade performance. Furthermore, the single-cycle line transfer suggested in prior studies adversely affects Level-1 Data Cache (L1 DC) area and energy efficiency. We propose a practical DFC that is accessed early in the pipeline and transfers a line over multiple cycles. Our DFC design improves performance and eliminates a substantial fraction of L1 DC accesses for loads, L1 DC tag checks on stores, and data translation lookaside buffer accesses for both loads and stores. Our evaluation shows that the proposed DFC can reduce the data access energy by 42.5% and improve execution time by 4.2%.