The Mips R10000 superscalar microprocessor
The Mips R10000 superscalar microprocessor
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DOI：
10.1109/40.491460
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发表时间：
1996-04
期刊：
影响因子：
3.6
通讯作者：
Kenneth C. Yeager
中科院分区：
文献类型：
--
作者：
Kenneth C. Yeager
Mips R10000是一款动态超标量微处理器，采用64位Mips 4指令集架构。它每个周期提取和解码四条指令，并动态地将它们发送到五个完全流水线的低延迟执行单元。指令可以在分支之外被推测性地获取和执行。指示完成后按顺序毕业。虽然执行是无序的，但处理器仍然提供顺序内存一致性和精确的异常处理。R10000专为高性能而设计，即使在内存局部性较差的大型实际应用中也是如此。通过推测执行，它计算内存地址并提前启动缓存重新填充。它的分层，非阻塞内存系统有助于隐藏内存延迟与两个级别的集关联，回写缓存。
The Mips R10000 is a dynamic, superscalar microprocessor that implements the 64-bit Mips 4 instruction set architecture. It fetches and decodes four instructions per cycle and dynamically issues them to five fully-pipelined, low-latency execution units. Instructions can be fetched and executed speculatively beyond branches. Instructions graduate in order upon completion. Although execution is out of order, the processor still provides sequential memory consistency and precise exception handling. The R10000 is designed for high performance, even in large, real-world applications with poor memory locality. With speculative execution, it calculates memory addresses and initiates cache refills early. Its hierarchical, nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches.