Power-Constrained Test Scheduling for Multi-Clock Domain SoCs
Power-Constrained Test Scheduling for Multi-Clock Domain SoCs
复制标题
多时钟域 SoC 的功耗受限测试调度
DOI：
10.1109/date.2006.244142
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
H. Fujiwara
中科院分区：
文献类型：
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作者：
T. Yoneda;Kimihiko Masuda;H. Fujiwara
提出了一种针对多时钟域片上系统的封装和测试访问机制设计方法。我们还提出了一种多时钟域SoC的测试调度算法，以最小化功耗约束下的测试时间。在所提出的方法中，我们使用虚拟TAM来解决核心和ATE之间的频率差距，并在保持核心的测试时间的情况下，降低测试过程中的核心功耗。实验结果表明，该方法不仅适用于多时钟域系统芯片，而且适用于单时钟域系统芯片
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a test scheduling algorithm for multi-clock domain SoCs to minimize test time under power constraint. In the proposed method, we use virtual TAM to solve the frequency gaps between cores and the ATE, and also to reduce power consumption of a core during test while maintaining the test time of the core. Experimental results show the effectiveness of our method not only for multi-clock domain SoCs, but also for single-clock domain SoCs with power constraints