Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver
Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver
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DOI：
10.1088/1674-4926/39/5/055002
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发表时间：
2018-05
影响因子：
5.1
通讯作者：
Binjie Ge;Yan Li;Han-Yeol Yu;Xiaoxing Feng
中科院分区：
文献类型：
--
作者：
Binjie Ge;Yan Li;Han-Yeol Yu;Xiaoxing Feng
This paper presents the design and implementation of quadrature bandpass sigma-delta modulator. A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and -1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2.
