Automated construction of a cycle-approximate transaction level model of a memory controller
Automated construction of a cycle-approximate transaction level model of a memory controller
复制标题
自动构建内存控制器的周期近似事务级模型
DOI：
10.1109/date.2012.6176653
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
Ulf Schlichtmann
中科院分区：
文献类型：
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作者：
V. Todorov;Daniel Mueller;H. Reinig;Ulf Schlichtmann
事务级(TL)模型是早期设计探索、性能评估和虚拟样机的关键。它们的速度和准确性使芯片上系统(SoC)设计评估和软件开发得以及早和快速进行。大多数器件只有寄存器传输级(RTL)模型，对于SoC模拟来说过于复杂。然而，将这些模型抽象为目标语言模型是一项具有挑战性的任务，特别是当RTL描述过于晦涩或不可访问的时候。这项工作提出了一种自动创建RTL存储器控制器组件的TL模型的方法。该设备被视为一个黑匣子，并使用大量模拟来获得结果，显示其时序行为。结果被分类为条件概率分布，这些分布在TL模型中被重复使用以近似RTL定时行为。该方法具有快速、准确的特点。由此得到的TL模型的执行速度大约快1200倍，最大测量平均定时偏差误差为7.66%。
Transaction level (TL) models are key to early design exploration, performance estimation and virtual prototyping. Their speed and accuracy enable early and rapid System-on-Chip (SoC) design evaluation and software development. Most devices have only register transfer level (RTL) models that are too complex for SoC simulation. Abstracting these models to TL ones, however, is a challenging task, especially when the RTL description is too obscure or not accessible. This work presents a methodology for automatically creating a TL model of an RTL memory controller component. The device is treated as a black box and a multitude of simulations is used to obtain results, showing its timing behavior. The results are classified into conditional probability distributions, which are reused within a TL model to approximate the RTL timing behavior. The presented method is very fast and highly accurate. The resulting TL model executes approximately 1200 times faster, with a maximum measured average timing offset error of 7.66%.