Empirical Quantitative Modeling of Threshold Voltage of Sub-50-nm Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor
Empirical Quantitative Modeling of Threshold Voltage of Sub-50-nm Double-Gate Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor
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DOI：
10.1143/jjap.45.3074
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发表时间：
2006-04
影响因子：
1.5
通讯作者：
Y. Tahara;Y. Omura
中科院分区：
文献类型：
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作者：
Y. Tahara;Y. Omura
利用流体动力学输运模型模拟了双栅绝缘体上硅金属氧化物半导体场效应晶体管（SOI MOSFET）的阈值电压特性。已经表明，在许多情况下，阈值电压随着SOI层厚度的减小而增加，这不是由于明显的量子效应。这源于阈值处表面电位的增加;表面电位的这种增加是物理上不可避免的结果，因为SOI层厚度的减小降低了每单位面积的反型层载流子密度。提出了阈值电压和阈值处表面电位的模型，并与详细的模拟结果进行了比较，验证了模型的有效性。我们还讨论了短沟道效应对表面电位的影响，并提出了漏致势垒降低模型。
We simulated the threhold voltage characteristics of an ultrathin double-gate (DG) silicon-on-insulator metal–oxide–semiconductor field-effect transistor (SOI MOSFET) using the hydrodynamic transport model. It has been shown that threshold voltage increases as SOI layer thickness is reduced in many cases, which is not due to a distinct quantum effect. This stems from an increase in surface potential at the threshold; this increase in surface potential is a physically inevitable result because a reduction in SOI layer thickness decreases inversion layer carrier density per unit area. We proposed models of threshold voltage and surface potential at the threshold, and their availabilities were confirmed by comparing what with the detailed simulation results. We also addressed the short-channel effect on surface potential and proposed a model of drain-induced barrier lowering.