HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
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DOI：
10.1145/3289602.3293910
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发表时间：
2019-02
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影响因子：
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通讯作者：
Yi-Hsiang Lai;Yuze Chi;Yuwei Hu;Jie Wang;Cody Hao Yu;Yuan Zhou;J. Cong;Zhiru Zhang
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文献类型：
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作者：
Yi-Hsiang Lai;Yuze Chi;Yuwei Hu;Jie Wang;Cody Hao Yu;Yuan Zhou;J. Cong;Zhiru Zhang
随着在严格的功率限制下追求提高计算性能，越来越需要用加速器（例如GPU和FPGA）将应用程序部署到异质硬件体系结构。但是，尽管这些异质计算平台已广泛使用，但它们很难编程，尤其是在FPGA中。结果，使用此类平台的使用仅限于具有专门硬件知识的一小部分程序员。为了应对这一挑战，我们引入了HeteroCl，这是一个由基于Python的域特异性语言（DSL）和FPGA键入的汇编流组成的编程基础架构。 HeteroCl DSL提供了一个干净的编程抽象，该抽象将算法规范与计算，数据类型和内存体系结构中的三种重要类型的硬件自定义类型分解。 Heterocl进一步捕获了这些不同的自定义技术之间的相互依存关系，使程序员能够以系统和生产的方式探索各种性能/领域/准确性权衡。此外，我们的框架通过针对空间体系结构模板（例如收缩阵列和具有数据流架构的模板）来为各种流行的工作负载产生高效的硬件实现。实验结果表明，HeterOCL允许程序员通过组合不同类型的硬件自定义和定位空间体系结构，同时保持算法代码完整，从而有效地探索了性能和准确性的设计空间。
With the pursuit of improving compute performance under strict power constraints, there is an increasing need for deploying applications to heterogeneous hardware architectures with accelerators, such as GPUs and FPGAs. However, although these heterogeneous computing platforms are becoming widely available, they are very difficult to program especially with FPGAs. As a result, the use of such platforms has been limited to a small subset of programmers with specialized hardware knowledge. To tackle this challenge, we introduce HeteroCL, a programming infrastructure composed of a Python-based domain-specific language (DSL) and an FPGA-targeted compilation flow. The HeteroCL DSL provides a clean programming abstraction that decouples algorithm specification from three important types of hardware customization in compute, data types, and memory architectures. HeteroCL further captures the interdependence among these different customization techniques, allowing programmers to explore various performance/area/accuracy trade-offs in a systematic and productive manner. In addition, our framework produces highly efficient hardware implementations for a variety of popular workloads by targeting spatial architecture templates such as systolic arrays and stencil with dataflow architectures. Experimental results show that HeteroCL allows programmers to explore the design space efficiently in both performance and accuracy by combining different types of hardware customization and targeting spatial architectures, while keeping the algorithm code intact.