A 7-nm FinFET 1.2-TB/s/mm$^{2}$ 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
A 7-nm FinFET 1.2-TB/s/mm$^{2}$ 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
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具有 0.7pJ/b 电感耦合接口（使用 Over-SRAM 线圈和曼彻斯特编码同步收发器）的 7-nm FinFET 1.2-TB/s/mm$^{2}$ 3D 堆叠 SRAM 模块
DOI：
10.1109/jssc.2022.3224421
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发表时间：
2022
影响因子：
5.4
通讯作者：
and T. Kuroda
中科院分区：
文献类型：
--
作者：
K. Shiba;M. Okada;A. Kosuge;M. Hamada;and T. Kuroda
在7纳米FinFET工艺中开发了用于3D堆叠静态随机存取存储器（SRAM）的0.7-pJ/位、8.5-Gb/s/链路电感耦合芯片间无线通信接口。一种新的物理放置方法，允许线圈放置在具有小磁场衰减的现成SRAM宏上，同时使用曼彻斯特编码和时钟比较器进行同步通信，以检测小摆幅信号，与基于硅通孔（TSV）的堆叠相比，SRAM芯片面积减少了26%。使用测试芯片确认了0.7 pJ/bit、8.5 Gb/s/链路的芯片间通信。使用该接口的4层3D堆叠SRAM模块的面积效率达到了1.2 TB/s/mm 2，比现有的3D堆叠SRAM提高了两个数量级。
A 0.7-pJ/bit, 8.5-Gb/s/link inductive coupling interchip wireless communication interface for a 3D- stacked static-random access memory (SRAM) has been developed in a 7-nm FinFET process. A new physical placement method that allows coils to be placed over off-the-shelf SRAM macros with small magnetic field attenuation, together with the use of synchronous communication using Manchester encoding and a clocked comparator to enable the detection of small-swing signals, achieves a 26% reduction in SRAM die area compared to through-silicon via (TSV)-based stacking. Interchip communication at 0.7 pJ/bit, 8.5 Gb/s/link was confirmed using test chips. A 4-hi 3D- stacked SRAM module using the proposed interface achieves a 1.2-TB/s/mm2area efficiency, representing a two orders-of-magnitude improvement over the state-of-the-art 3D- stacked SRAM.