Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core
复制标题
系统LSI加载的FPGA-IP核的物理故障检测和恢复方法
DOI：
10.1587/transinf.2016awi0005
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
T. Sueyoshi
中科院分区：
文献类型：
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作者：
Motoki Amagasaki;Yuki Nishitani;Kazuki Inoue;M. Iida;M. Kuga;T. Sueyoshi
容错是可靠性关键系统中使用的系统LSI的重要特性。虽然冗余技术通常用于提供容错，但是这些技术具有显著的硬件成本。然而，FPGA可以很容易地提供高可靠性，由于他们的重新配置能力。即使发生故障，所实现的电路也可以通过重新配置到FPGA的无故障区域来正确执行。在本文中，我们研究了加载在SoC中的FPGA-IP核，并介绍了一种基于故障检测和恢复的容错技术作为CAD级的方法。为了检测故障位置，我们增加了一条路线，在早期的研究中提出的制造测试方法和识别故障区域。此外，我们执行故障恢复的逻辑瓦片和多路复用器的水平，使用重新配置。测试结果表明，该方法能够完全识别和避免相对于路由区的故障区域。关键词：容错，故障恢复，FPGA-IP
Fault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area. key words: fault tolerant, fault recovery, FPGA-IP