Security design against stealthy attacks on power system state estimation: A formal approach

Security design against stealthy attacks on power system state estimation: A formal approach
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针对电力系统状态估计隐形攻击的安全设计:一种形式化方法

DOI:
10.1016/j.cose.2019.03.022
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发表时间:
2019
影响因子:
5.6
通讯作者:
Al-Shaer, Ehab
Al-Shaer, Ehab
中科院分区:
计算机科学3区
文献类型:
--
作者:
Rahman, Mohammad Ashiqur;Datta, Amarjit;Al-Shaer, Ehab

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状态估计对于安全、可靠、高效地维护电网是非常重要的。如果状态估计不受保护,攻击者可能会危害仪表或通信系统并引入错误测量,从而规避现有的不良数据检测(BDD)算法并导致错误的状态估计。这种攻击是隐蔽的,广为人知的是未检测到的虚假数据注入(UFDI)攻击。攻击者在知识、能力、资源和攻击目标方面受到不同属性的限制,这些属性对于实现潜在的攻击矢量和安全措施是重要的。在这篇文章中,我们提出了一个形式化的框架,用于自动合成安全体系结构,以保护网格免受潜在的状态估计UFDI攻击。在这种方法中,我们首先根据网格拓扑、电气属性和不同的攻击属性来形式化UFDI攻击。该模型的解派生出形式化场景中存在的攻击向量。这些攻击向量被第二个形式模型,即安全体系结构合成模型考虑,以设计安全措施(即,要防止错误数据注入的一组测量)。通过对形式化模型进行并行和分步执行来提高安全体系结构综合机制的性能。我们通过案例研究演示了所提出的机制,并通过在不同的IEEE测试系统上运行实验来评估所提出的模型的性能。
State estimation is very important for securely, reliably, and efficiently maintaining a power grid. If state estimation is not protected, an attacker can compromise meters or communication systems and introduce false measurements, which can evade existing Bad Data Detection (BDD) algorithms and lead to incorrect state estimation. This kind of attack is stealthy and widely known as an Undetected False Data Injection (UFDI) attack. Attackers are limited by different attributes, in terms of knowledge, capabilities, resources, and attack targets, that are important to consider for realizing the potential attack vectors and, thereby, the security measures. In this paper, we present a formal framework for automatic synthesis of security architectures that will guard the grid against potential UFDI attacks on state estimation. In this approach, we first formalize UFDI attacks with respect to the grid topology, electrical properties, and different attack attributes. The solution to the model derives the attack vectors that exist in the formalized scenario. These attack vectors are considered by a second formal model, the security architecture synthesis model, to design the security measures (i.e., a set of measurements to be protected against false data injection). We enhance the performance of the security architecture synthesis mechanism by performing parallel and stepped execution of the formal models. We demonstrate the proposed mechanism through case studies and evaluate the performance of the proposed model by running experiments on different IEEE test systems.
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DOI: 10.32657/10356/69105
发表时间: 2016
期刊: 2016 IEEE International Conference on Power System Technology (POWERCON)
影响因子: --
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期刊: 2015 54th IEEE Conference on Decision and Control (CDC)
影响因子: --
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