Photonic networks-on-chip for future generations of chip multiprocessors
Photonic networks-on-chip for future generations of chip multiprocessors
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DOI：
10.1109/tc.2008.78
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发表时间：
2008-09-01
影响因子：
3.7
通讯作者：
Carloni, Luca P.
中科院分区：
文献类型：
--
作者：
Shacham, Assaf;Bergman, Keren;Carloni, Luca P.
下一代芯片多处理器（cmp）的设计和性能将受到单个芯片耗散的有限功率的限制。我们提出片上光子网络（NoC）作为一种解决方案，以减少片内和片外通信对整体功耗预算的影响。光波导的低损耗特性与比特率透明性相结合，使得光子互连网络能够比仅基于电子信号的互连网络提供更高的带宽和更低的延迟，并且功耗显着降低。我们解释了为什么片上光子通信最近成为一个可行的机会，并探讨了实现其实施需要解决的挑战。本文介绍了一种新型的混合微体系结构，它将宽带光子电路交换网络与电子覆盖分组交换控制网络相结合。该设计充分利用了每种技术的优势，为芯片上交换的不同类型的消息提供了灵活的解决方案；大信息通过光子网络更有效地传递，而短信息则以最小的功耗以电子方式传递。我们解决了关键的设计问题，包括拓扑、路由算法、死锁避免和路径设置/拆除程序。我们展示了用POINTS获得的实验结果，POINTS是一个事件驱动模拟器，专门用于分析所提出的设计思想，以及光子与电子NoC的比较功率分析。总的来说，这些结果证实了未来几代cmp的独特优势，这些优势可以通过将光学以光子noc的形式引入芯片中来实现。
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intrachip and off- chip communication on the overall power budget. The low loss properties of optical waveguides, combined with bit- rate transparency, allow for a photonic interconnection network that can deliver considerably higher bandwidth and lower latencies with significantly lower power dissipation than an interconnection network based only on electronic signaling. We explain why on- chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid microarchitecture for NoCs that combines a broadband photonic circuit- switched network with an electronic overlay packet- switched control network. This design leverages the strength of each technology and represents a flexible solution for the different types of messages that are exchanged on the chip; large messages are communicated more efficiently through the photonic network, while short messages are delivered electronically with minimal power consumption. We address the critical design issues including topology, routing algorithms, deadlock avoidance, and path- setup/ teardown procedures. We present experimental results obtained with POINTS, an event- driven simulator specifically developed to analyze the proposed design idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.