Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
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DOI:
10.1109/tvlsi.2018.2812700
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发表时间:
2018-03
影响因子:
2.8
通讯作者:
Jinghua Yang;A. Dengi;S. Vrudhula
中科院分区:
文献类型:
--
作者:
Jinghua Yang;A. Dengi;S. Vrudhula
Systems powered by harvested energy must consume very low power and withstand frequent interruptions in power. Nonvolatile logic (NVL) addresses the latter by saving the system state in flipflops enhanced with spin-transfer torque magnetic tunnel junctions (STT-MTJs) as the nonvolatile storage devices. Manufacturing variations in the STT-MTJs and in CMOS transistors significantly reduce yield, leading to overdesign and high-energy consumption. A detailed analysis of the design tradeoffs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Next, efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly $5\times $ more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. Also included are the energy consumption of the proposed NVFF designs when used in two larger function blocks. Experimental results were based on a commercial 40-nm process design kit, and HSPICE simulations with foundry supplied statistical models and data.