Waveform relaxation techniques and their parallel implementation
Waveform relaxation techniques and their parallel implementation
复制标题
波形弛豫技术及其并行实现
DOI：
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发表时间：
1985
期刊：
影响因子：
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通讯作者：
Jacob K. White
中科院分区：
文献类型：
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作者：
A. Sangiovanni;Jacob K. White
由于集成电路（IC）的制造成本很高，因此使用仿真来验证设计是很重要的。模拟集成电路设计的方法多种多样，但最精确的方法是构造描述给定电路的非线性常微分方程系统，并用数值积分方法求解该系统。这种方法被称为电路仿真，计算成本很高，特别是应用于大型电路时。为了减少模拟大型MOS电路所需的计算时间，基于松弛技术的数值积分算法得到了发展。这些技术可以减少仿真时间多达一个数量级的标准电路仿真程序。此外，它们特别适合并行实现。在本文中，我们将重点讨论波形松弛（WR）算法族。在这个家族的算法将被审查，收敛定理将提供，并提出他们在并行处理器上的实现。
Because of the high cost of fabricating an Integrated Circuit(IC), it is important to verify the design using simulation. There are a wide variety of techniques for simulating integrated circuit designs, but the most accurate is to construct the system of nonlinear ordinary differential equations that describe a given circuit, and solve the system with a numerical integration method. This approach, referred to as circuit simulation, is computationally expensive, particularly when applied to large circuits. To reduce the computation time required to simulate large MOS circuits, new numerical integration algorithms based on relaxation techniques have been developed. These techniques can reduce the simulation time as much as an order of magnitudes over standard circuit simulation programs. In addilion, they are particularly suited for parallel implementation. In this paper we will focus on the Waveform Relaxation (WR) family of algorithms. Algorithms in this family will be reviewed, convergence theorems will be offered, and their implementation on a parallel processor presented.