CMOS pulse-modulation circuit implementation of phase-locked loop neural networks
CMOS pulse-modulation circuit implementation of phase-locked loop neural networks
复制标题
锁相环神经网络的 CMOS 脉冲调制电路实现
DOI：
10.1109/iscas.2008.4541882
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
T. Morie
中科院分区：
文献类型：
--
作者：
Daisuke Atuti;K. Nakada;T. Morie
在本文中，我们应用脉冲调制电路技术来实现由Hoppensteadt和Izhikevich提出的锁相环（PLL）神经网络。PLL神经网络是作为联想记忆模型的振荡神经网络，并且它被表示为具有周期相位变量和周期非线性相互作用的耦合相位振荡器。在我们的电路实现中，相位变量及其求和和相减由脉宽调制（PWM）信号表示。通过使用由PWM信号转换的脉冲相位调制（PPM）信号采样的非线性电流波形来实现相互作用。我们已经设计了一个元件电路和模拟两个耦合这样的电路与SPICE使用台积电0.25妈妈的器件参数。结果表明，在不同的工作频率下，元件电路的同步与同相和反相依赖于耦合强度。元件电路在提取电路之间的相位差方面具有优势。这将有助于通过使用相位差的任意尖峰定时依赖可塑性（STDP）规则来实现学习。
In this paper, we have applied the pulse-modulation circuit technique to implement phase-locked loop (PLL) neural networks proposed by Hoppensteadt and Izhikevich. The PLL neural network is an oscillatory neural network as a model of associative memory, and it is represented as coupled phase oscillators with periodic phase variables and periodic nonlinear interactions. In our circuit implementation, the phase variables and their summation and subtraction are represented by pulse- width modulation (PWM) signals. The interactions are realized by using nonlinear current waveform sampled with pulse-phase modulation (PPM) signals converted from the PWM signals. We have designed an element circuit and simulated two coupled such circuits with SPICE using the TSMC 0.25 mum device parameters. The results demonstrate that the element circuits synchronized with in- and anti-phase depending on coupling strength at different operation frequencies. The element circuit has an advantage in extracting phase difference between the circuits. This will facilitate implementing of learning by arbitrary spike-timing dependent plasticity (STDP) rules using the phase difference.
非线性动力系统的脉冲调制技术和具有任意一维映射的 CMOS 混沌电路
DOI：
--
发表时间：
2004
期刊：
IEICE Trans. Electron. E87-C
影响因子：
--
作者：
T.Morie;K Murakoshi;M Nagata;A.Iwata
通讯作者：
A.Iwata