Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for
Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for
复制标题
具有自动回避电路的 ReRAM 新型功耗降低技术
DOI：
10.1155/2012/181395
复制
发表时间：
2012
影响因子：
0.4
通讯作者：
and Akio Kitagawa
中科院分区：
文献类型：
--
作者：
Takaya Handa;Yuhei Yoshimoto;Kazuya Nakayama;and Akio Kitagawa
低功耗操作对于ReRAM器件非常有利。然而，诸如对低电阻状态（LRS）器件的置位操作和对高电阻状态（HRS）器件的复位操作的浪费的复位不仅导致功率的增加，而且由于重复重写而导致写入周期的劣化。因此，在本文中，我们提出了一种新的自动避免电路，用于处理使用感测放大器的浪费性噪声，并通过进行电路仿真来估计能耗降低率。因此，该电路有助于可靠地避免浪费的重复操作，使用VSRC和CSRC分别减少约99%和97%的浪费能量。
Low‐power operations can be great advantageous for ReRAM devices. However, wasteful overwriting such as the SET operation to low‐resistance state (LRS) device and the RESET operation to high‐resistance state (HRS) device causes not only an increase in power but also the degradation of the write cycles due to repeatedly rewriting. Thus, in this paper, we proposed a novel automatic avoidance circuit for dealing with wasteful overwriting that uses a sense amplifier and estimated the energy consumption reduction rate by conducting a circuit simulation. As a result, this circuit helped to reliably avoid the wasteful overwriting operation to reduce about 99% and 97% of wasteful energy using VSRC and CSRC, respectively.