A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network
A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network
复制标题
基于多级单元 STT-MRAM 的二元卷积神经网络内存计算加速器
DOI：
10.1109/tmag.2018.2848625
复制
发表时间：
2018-11-01
影响因子：
2.1
通讯作者：
Wei, Shaojun
中科院分区：
文献类型：
--
作者：
Pan, Yu;Ouyang, Peng;Wei, Shaojun
由于二进制卷积神经网络（BCNN）中加法运算占主导地位的计算和简化的网络，它很有希望用于要求超低功耗的物联网场景。通过充分利用多级单元（MLC-STT）自旋矩转移磁随机存储器（STT-MRAM）的内存计算优势和低功耗设计，提出了一种基于MLC-STT计算的内存计算架构，实现BCNN的卷积运算，进一步降低功耗。仿真结果表明，与电阻式随机存取存储器（RRAM）和自旋轨道转矩STT-MRAM为基础的同行相比，本文提出的架构降低了类似的35倍和59%的功耗在修改后的美国国家标准与技术研究所的数据集，分别。
Due to additive operation's dominated computation and simplified network in binary convolutional neural network (BCNN), it is promising for Internet of Things scenarios which demand ultralow power consumption. By means of fully exploiting the in-memory computing advantages and low current consumption design using multilevel cell (MLC) spin-toque transfer magnetic random access memory (STT-MRAM), this paper proposes an MLC-STT-computing in-memory-based computing in-memory architecture to achieve convolutional operation for BCNN to further reduce the power consumption. Simulation results show that compared with the resistive random access memory (RRAM)- and spin orbit torque-STT-MRAM-based counterparts, the architecture proposed in this paper reduces power consumption by similar to 35x and 59% in Modified National Institute of Standards and Technology data set, respectively.