Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform
Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform
复制标题
针对第三轮 SHA-3 决赛入围者 Grostl 在 FPGA 平台上进行基准测试的可靠硬件架构
DOI：
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发表时间：
2011
期刊：
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通讯作者：
A. Reyhani
中科院分区：
文献类型：
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作者：
Mehran Mozaffari Kermani;A. Reyhani
SHA-3候选人的第三轮比赛正在进行2012年的获胜职能。尽管已经非常关注这些候选人的绩效和安全性，但迄今为止尚未提出提高其可靠性的方法。在本文中，我们首次提出了一种高性能方案，用于检测SHA-3圆形三候选人Grostl，该方案受到高级加密标准（AES）的启发。我们通过为该SHA-3第三轮决赛的不同变换的预测签名提出封闭式签名，提出了一个低空故障检测方案。这些签名被得出以达到低开销，并包括一个或多位均等和字节/单词范围的预测签名。 Xilinx virtex-6 FPGA家族实现了拟议的可靠硬件体系结构，以基准其硬件和时机特征。我们的评估结果显示了拟议方案的高误差覆盖率和可接受的开销。
The third round of competition for the SHA-3 candidates is ongoing to select the winning function in 2012. Although much attention has been devoted to the performance and security of these candidates, the approaches for increasing their reliability have not been presented to date. In this paper, for the first time, we propose a high-performance scheme for fault detection of the SHA-3 round-three candidate Grostl which is inspired by the Advanced Encryption Standard (AES). We propose a low-overhead fault detection scheme by presenting closed formulations for the predicted signatures of different transformations of this SHA-3 third-round finalist. These signatures are derived to achieve low overhead and include one or multi-bit parities and byte/word-wide predicted signatures. The proposed reliable hardware architectures for Grostl are implemented on Xilinx Virtex-6 FPGA family to benchmark their hardware and timing characteristics. The results of our evaluations show high error coverage and acceptable overhead for the proposed scheme.