Back-End Layout Reflection for Test Chip Design
Back-End Layout Reflection for Test Chip Design
复制标题
测试芯片设计的后端布局反思
DOI：
--
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
R. D. Blanton
中科院分区：
文献类型：
--
作者：
Z. Liu;R. D. Blanton
在先进技术节点，布局特征和工艺之间的复杂交互可能导致降低良率的可制造性问题。由于随机逻辑固有的大量布局几何形状，在成品率斜坡期间越来越多地采用仅逻辑测试芯片。这项工作描述了一种设计方法，将复杂的布局几何形状到一个最佳的可测试的全流程逻辑测试芯片。测试芯片，基准测试，和实际产品设计之间的性能比较实验证明了该方法的有效性。具体而言，我们的测试芯片实现了对各种故障模型的100%覆盖，平均而言，与各种基准和产品设计相比，集成了感兴趣的布局几何形状，同时减少了96%的布局面积和63%的导线长度。
At advanced technology nodes, complex interactions between layout features and the process can lead to manufacturability issues that reduce yield. Due to the huge number of layout geometries inherent to random logic, logic-only test chips are increasingly employed during yield ramp. This work describes a design methodology that incorporates complex layout geometries into an optimally testable full-flow logic test chip. Experiments comparing properties among test-chip, benchmark, and actual product designs demonstrate the efficacy of the methodology. Specifically, our test chips achieve 100% coverage for various fault models, and on average, incorporate the layout geometries of interest while being 96% less layout area and 63% less wire length compared to various benchmark and product designs.